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Introduction to MOSFETs

Module by: Bill Wilson

Summary: Introduction to MOSFET, a device called Metal-Oxide-Semiconductor Field Effect Transistor.

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We now move on to another three terminal device - also called a transistor. (In truth this device really has at least four, and probably five, terminals, but we will leave the subtle details for a later time.) This transistor, however, works on much different principles than does the bipolar junction transistor of the last chapter. We will now focus on a device called the Field Effect Transistor, or Metal-Oxide-Semiconductor Field Effect Transistor or simply, the MOSFET. Consider Figure 1.

Figure 1: The start of a field effect transistor

Here we have a block of silicon, doped p-type. Into it we have made two regions which are doped n-type. To each of those n-type regions we attach a wire, and connect a battery between them. If we try to get some current, I, to flow through this structure, nothing will happen, because the n-p junction on the RHS is reverse biased (We have the positive lead from the battery going to the n-side of the p-n junction). If we attempt to remedy this by turning the battery around, we will now have the LHS junction reverse biased, and again, no current will flow. If, for whatever reason, we want current to flow, we will need to come up with some way of forming a layer of n-type material between one n-region and the other. This will then connect them together, and we can run current in one terminal and out the other.

To see how we will do this, let's do two things. First we will grow a layer of SiO₂ (silicon dioxide, or just plain "oxide") on top of the silicon. (This turns out to be relatively easy, we just stick the wafer in an oven with some oxygen flowing through it, and heat everything up to about 1100°C for an hour or so, and we end up with a nice, high-quality insulating SiO₂ layer on top of the silicon). On top of the oxide layer we then deposit a conductor, which we call the gate. In the "old days" the gate would have been a layer of aluminum (Hence the "metal-oxide-silicon" or MOS name). Today, it is much more likely that a heavily doped layer of polycrystalline silicon (polysilicon, or more often just "poly") would be deposited to form the gate structure. (I guess "POS" sounded funny to people in the field, because it never caught on as a name for these devices). Polysilicon is made from the reduction of a gas, such as silane ( SiH₄) through the reaction

SiH₄(g)→Si (s)+2H₂(g) (1)

The silicon is polycrystalline (composed of lots of small silicon crystallites) because it is deposited on top of the oxide, which is amorphous, and so it does not provide a single crystal "matrix" which would allow the silicon to organize itself into one single crystal. If we had deposited the silicon on top of a single crystal silicon wafer, we would have formed a single crystal layer of silicon called an epitaxial layer1. This is sometimes done to make structures for particular applications. For instance, growing a n-type epitaxial layer on top of a p-type substrate permits the fabrication of a very abrupt p-n junction.

1. Epitaxy comes from the Greek, and it just means "ordered upon". Thus an epitaxial layer is one which follows the order of the substrate on which it is grown.

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This work is licensed by Bill Wilson. See the Creative Commons License about permission to reuse this material.

Last edited by Elizabeth Gregory on Jun 20, 2003 12:00 am GMT-5.

+ نوشته شده در شنبه یازدهم اسفند 1386ساعت 21:5 توسط Sciport |

JFET

Module by: Bill Wilson

Summary: How JFET transistors work.

There is a lot more that we could do with field effect devices, but it is probably time to move on to new topics. For one final point however, we might just look at something called the JFET, or junction field effect transistor. The JFET structure looks like Figure 1. It consists of a piece of p-type silicon, into which two n-type regions have been diffused. However, instead of being both on the same surface, as with a MOSFET, the two regions are opposite one another on either side of the crystal. In cross-section, the JFET looks like Figure 2. We also show the biasing here.

Figure 1: JFET

Figure 2: Biasing a JFET

The two n-regions are connected together, and are reverse biased with respect to the p-type substrate. A second battery, V_ds is used to pull current out of the source, by applying a negative voltage between the drain and the source. The reverse biased n-p junctions creates a depletion region which extends into the p-type material through which the holes travel as they go from source to drain (a channel?). By adjusting the value of V_gs, one can make the depletion region smaller or larger, thus increasing or decreasing the drain current.

The observant student will also note that the polarity of the V_ds battery makes it so that there is more reverse bias across the p-n junctions at the drain end of the channel than at the source end. Thus, a more accurate depiction of the JFET would be what is shown in Figure 3. When the drain/source voltage gets large enough, the two depletion regions will join together, and, just as with the MOSFET, the channel pinches off, as shown in Figure 4.

Figure 3: Depletion region controls current

Figure 4: Pinch-Off

Surprising as it may seem, when you work out the equations which describe how the depletion region extends with V_gs and how the pinch-off mechanism changes I_D, you end up with behavior, and equations, which are quite similar to those of a depletion-mode MOSFET.

Using JFETs is a little more cumbersome than a normal MOSFET. You must make sure that the gate-substrate junction always remains reverse biased, and since the JFET can only be a depletion-mode device, you have to have a voltage on the gate if you want to turn the transistor off. The JFET does have one advantage over the MOSFET however. A while back we calculated the value for C_ox the oxide capacitance and found that it was on the order of 10^-7

cm²

. A typical MOSFET gate might be 1 μm long by 20 μm wide, and so it would have a gate area of 20 μm² or 2×10^-7 cm². Thus, the total gate capacitance is only about 10^-14F.

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